1. Field of Invention
The present invention relates to a non-volatile memory, and more particularly, to a method of using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure.
2. Discussion of Background
Numerous non-volatile memory devices have been developed by the semiconductor industry for various computer and digital communications applications. In particular, a variety of non-volatile memory devices with oxide-nitride-oxide (ONO) structures have been developed. An example of a typical non-volatile memory cell with an ONO structure comprises a semiconductor substrate with source and drain regions, a channel region formed close to the surface of the semiconductor substrate between the source and the drain when electrical conduction occurs between the source and the drain, an oxide-nitride-oxide (ONO) film on top of the substrate surface between the source and the drain, and a gate on top of the ONO film. The ONO film comprises three layers including a first oxide layer on top of the substrate surface between the source and the drain, a nitride layer on top of the first oxide layer, and a second oxide layer on top of the nitride layer. The nitride layer in the ONO film is capable of trapping electrons which are generated in the channel region of the semiconductor substrate during a programming operation.
The conventional non-volatile memory cell with an ONO structure is programmed by generating hot electrons in the vicinity of the drain region in the substrate and injecting the hot electrons into the ONO film. More specifically, the hot electrons are injected into a portion of the nitride layer near the drain of the non-volatile memory cell. Thereafter, since the nitride layer is an insulator, the hot electrons tend to remain in the portion of the nitride layer near the drain without dispersing into, for example, the center of the nitride layer.
The presence of the trapped hot electrons in the portion of the nitride layer adjacent to the drain signifies that at least the drain side of the non-volatile memory cell is xe2x80x9cprogrammed.xe2x80x9d The non-volatile memory cell with a typical ONO structure may be programmed by applying high positive voltages to the gate and the drain regions while grounding the source of the non-volatile memory cell. This results in hot electrons being injected into the portion of the nitride layer adjacent to the drain. This technique is commonly referred to as hot electron injection or channel hot electron programming.
FIG. 1 shows a cross-sectional view of a non-volatile memory cell 2 which comprises a substrate 4, an oxide-nitride-oxide (ONO) film 6 comprising a first oxide layer 8 on top of the substrate 4, a nitride layer 10 of top of the first oxide layer 8, and a second oxide layer 12 on top of the nitride layer 10. A polysilicon gate 14 is provided on top of the second oxide layer 12. Portions of the substrate 4 are doped with a group V element, such as arsenic, to form a source region 16 and a drain region 18. The source and drain regions 16 and 18 may be produced by implanting arsenic into the substrate 4 to a depth in the range of about 300 xc3x85 to about 600 xc3x85. The ONO film 6 is positioned on top of a surface portion 20 of the substrate 4 between the source region 16 and the drain region 18.
The first oxide layer 8, which is also called a tunnel oxide layer, is positioned directly on top of the surface portion 20 of the substrate 4 between the source region 16 and the drain region 18. When conduction occurs between the source region 16 and the drain region 18, a channel is formed in the substrate 4 close to the surface 20 between the source region 16 and the drain region 18. The first oxide layer 8 may have a thickness on the order of about 75 xc3x85.
The nitride layer 10, which is positioned on top of the first oxide layer 8, is capable of trapping hot electrons 32 generated in the channel and injected into portions 34, 36 of the nitride layer 10 near the drain region 18 during a typical programming operation. The nitride layer 10 may have a thickness on the order of about 75 xc3x85. The second oxide layer 12, which is positioned on top of the nitride layer 10, has a thickness typically on the order of about 100 xc3x85. The polysilicon gate 14, which is positioned on top of the second oxide layer 12, may be a conventional polysilicon gate which serves as a control gate for the non-volatile memory cell 2. The ONO film 6, which comprises the first oxide layer 8, the second oxide layer 12 and the nitride layer 10 sandwiched between the first and second oxide layers 8 and 12, may be fabricated by using conventional techniques known to a person skilled in the art.
FIG. 1 further shows portions of cross-sectional views of additional memory cells 22 and 24 adjacent to the non-volatile memory cell 2 in a non-Docket volatile memory array. The non-volatile memory cells 22 and 24 each have device structures identical to the non-volatile memory cell 2 described above. Further, adjacent non-volatile memory cells share a common arsenic-doped region which serves as the drain for one cell and as the source for the other cell. For example, the arsenic-doped region 16, which serves as the source for the non-volatile memory cell 2, also serves as the drain for the non-volatile memory cell 22. Similarly, the arsenic-doped region 18, which serves as the drain for the non-volatile memory cell 2, also serves as the source for the non-volatile memory cell 24.
FIG. 1 further shows a typical electron charge distribution in the substrate 4 after a typical programming operation in which channel hot electrons are generated in the substrate 4 and then injected and subsequently trapped in the nitride layer 10. After the non-volatile memory cell 2 is programmed, negative charge is formed in the portion of the substrate 4 beneath the substrate surface 20 between the source region 16 and the drain region 18. During the channel hot electron programming operation, electrons trapped in this substrate region have an electron charge distribution that is dependent upon the gate and drain voltages applied to the non-volatile memory cell 2 and the doping profiles for the source region 16 and the drain region 18.
More specifically, FIG. 1 shows an example of a typical electron charge distribution 26 in the portion of the substrate 4 between the source region 16 and the drain region 18 of the non-volatile memory cell 2 in which both the drain side and the source side are programmed using channel hot electron programming. The negative charge in the substrate 4 is relatively concentrated in a first region 28 adjacent to the source region 16 and in a second region 30 adjacent to the drain region 18.
However, hot electron injection is a stochastic or probabilistic event. Under normal operating conditions, hot electrons are most likely to be injected into the portion of the nitride layer 10 near the drain and least likely to be injected into the center portion of the nitride layer 10. Under normal operating conditions, very few hot electrons are injected into the center portion of nitride layer 10. The few hot electrons thus trapped in the center portion of nitride layer 10 have a minimal effect on the operating life of the non-volatile memory.
Under over-programming conditions, however, the life of the non-volatile memory cell having an ONO structure may be reduced to as few as several thousand program-erase cycles. Over-programming conditions, such as excessively long programming times or certain combinations of gate and drain bias voltages (e.g., a small differential voltage between the gate and drain voltages), increase the likelihood that hot electrons are injected into the center portion of nitride layer 10 with every programming operation.
For instance, if over-programming conditions were to result in one electron being injected into the center portion of nitride layer 10 every one thousand programming cycles, as opposed to one electron every one hundred thousand programming cycles, then a mere one million programming cycles would result in one thousand electrons being trapped in the center portion of nitride layer 10. The presence of these one thousand electrons, for example, may increase the threshold voltage VT of the non-volatile memory cell to a point where the cell can no longer be read.
Given certain process variations, the charge trapped in the center portion of nitride layer 10 may be sufficient to cause undesirable shifts in the threshold voltage in as few as several thousand program-erase cycles. Accordingly, there is a need for a method of preventing or limiting over-programming in non-volatile memory cells having ONO structures when hot carriers are used for programming. There is a further need for a method of minimizing the programming time of the non-volatile memory cells having ONO structures while increasing cell endurance and reliability.
In accordance with the present invention, roughly described, a method for programming a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure comprises the steps of applying a first train of voltage pulses to the drain of the non-volatile memory cell and applying a second train of voltage pulses to the gate of the non-volatile memory cell, the first train of voltage pulses being in phase with the second train of voltage pulses. In one embodiment, the amplitude of successive voltage pulses of at least one of the first and second trains of voltage pulses varies with time. In another embodiment, first and second trains of voltage pulses have variable first and second duty cycles, respectively. In another embodiment, the first and second duty cycles are varied such that the first and second trains of voltage pulses are transformed into corresponding first and second continuous voltage ramps.